This invention relates, in general, to decoding circuits, and more particularly to a block deselect circuit used in block architected static random access memories (SRAMs) built for compiler applications.
A SRAM compiler is a computer program which can synthesize different configurations of memory (variable wordwidth and number of words in the memory) for a SRAM. A SRAM compiler program creates a netlist of the memory, simulates the worst case delay path through the memory to generate timing information, builds a symbol of the SRAM for placement in a schematic, builds a simulation model with the timing information, creates a physical layout of the SRAM, builds a routing abstraction of the SRAM, and creates a power grid structure for the SRAM. The SRAM compiler is used to generate memories for application specific integrated circuits (ASICs), wherein the SRAM is only one component of many used in the design of the integrated circuit.
Initial attempts at building compilable decode stages focused on the extremely fast NAND and NOR decode stages used on full custom SRAMs for the consumer market. Although fast, the NAND and NOR decode stages proved cumbersome when implemented in a compiler for synthesizing random SRAM configurations. The computer code necessary to write the synthesis programs proved to be extremely complex, resource intensive, and take considerable development time. The standard approach was abandoned for new approaches developed to simplify building a compiler based memory.
First generation SRAM compilers and more specifically the decode stages, were designed to simplify the synthesis of the decode stage and the construction of the physical layout. The SRAM compilers were designed having a single block of memory which is not optimal for large memory size performance. Although compilers are capable of synthesizing a SRAM for most applications it has become evident that users expect performance levels and SRAM densities equivalent to what is offered in the full custom SRAM market place. Most compiled SRAMs are much slower than full custom designs due to the compromises in building a configurable circuit.
One method for enhancing the speed of the SRAM is to divide a large single block of memory into smaller individual blocks of memory. How the memory is accessed depends on the decoding scheme. Each block of memory can be accessed separately or multiple blocks can be accessed simultaneously. An additional stage of decoding must be added to the SRAM to access the individual memory blocks, but performance is gained by reducing parasitic capacitance and resistance associated with the memory block due to the smaller memory block size, thereby increasing speeds of the circuits which drive the smaller loads. This is known as a block architected SRAM. Adding the extra circuitry needed to form the block architected SRAM increases the complexity of a compiler program. There is a need for a decode circuit which simplifies compilability yet is compatible with a block architected SRAM design, and has performance similar to full custom block architected SRAM designs.